20 lines
498 B
Systemverilog
20 lines
498 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int array_bad[0]; // <--- Error: Must be positive size
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int array2_bad[-1]; // <--- Error: Must be positive size
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localparam X = 32'bz;
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logic [X:0] x; // <--- Error: X range
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sub #(1) u_sub ();
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endmodule
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module sub #(
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parameter SIZE = 0
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);
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int ignore[SIZE];
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endmodule
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