49 lines
1.3 KiB
Systemverilog
49 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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class C;
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task t;
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int c_no_has_init = 1; // Ok
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automatic int c_automatic_has_init = 1; // Ok
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static int c_static_has_init = 1; // Ok
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endtask
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endclass
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always @(posedge clk) begin
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int implicit_warn = 1; // <--- Warning: IMPLICITSTATIC
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localparam int OK = 2; // Ok
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end
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task t_implicit_static();
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int t_no_has_init = 1; // <--- Warning: IMPLICIT STATIC
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automatic int t_automatic_has_init = 1; // Ok
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static int t_static_has_init = 1; // Ok
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localparam int ONE = 1; // Ok
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++t_no_has_init;
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endtask
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function int f_implicit_static();
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int f_no_has_init = 1; // <--- Warning: IMPLICIT STATIC
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automatic int f_automatic_has_init = 1; // Ok
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static int f_static_has_init = 1; // Ok
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localparam int ONE = 1; // Ok
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++f_no_has_init;
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return ONE;
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endfunction
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initial begin
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int i_no_has_init = 1; // <--- Warning: IMPLICIT STATIC
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automatic int i_automatic_has_init = 1; // Ok
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static int i_static_has_init = 1; // Ok
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$finish;
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end
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endmodule
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