33 lines
678 B
Systemverilog
33 lines
678 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Risto Pejasinovic
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// SPDX-License-Identifier: CC0-1.0
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module submod2 ();
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endmodule
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module submod #() ();
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if (1) begin : submod_gen
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wire l1_sig;
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if (1) begin : nested_gen
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submod2 submod_nested ();
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end
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submod2 submod_l1 ();
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end
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submod2 submod_l0 ();
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endmodule
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module test ();
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genvar N;
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generate
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for (N = 0; N < 2; N = N + 1) begin : FOR_GENERATE
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submod submod_for ();
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if (1) begin
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submod submod_2 ();
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end
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submod submod_3 ();
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end
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endgenerate
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endmodule
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