71 lines
1.6 KiB
Systemverilog
71 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2004 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc;
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initial cyc = 0;
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wire signed [7:0] sgn_wide;
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wire [7:0] unsgn_wide;
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// The instantiation will Z extend, not sign extend
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// verilator lint_off WIDTH
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sub sub (
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.clk,
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.sgn(sgn_wide),
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.unsgn(unsgn_wide),
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.iss(3'sh7),
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.isu(3'h7),
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.ius(3'sh7),
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.iuu(3'h7)
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);
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// verilator lint_on WIDTH
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("out: 'b%b 'b%b\n", sgn_wide, unsgn_wide);
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`endif
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if (sgn_wide[2:0] != 3'sh7) $stop;
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if (unsgn_wide[2:0] != 3'h7) $stop;
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// Simulators differ here.
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if (sgn_wide !== 8'sbzzzzz111 // z-extension - NC
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&& sgn_wide !== 8'sb11111111)
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$stop; // sign extension - VCS
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if (unsgn_wide !== 8'sbzzzzz111 && unsgn_wide !== 8'sb00000111) $stop;
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cyc <= cyc + 1;
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if (cyc == 3) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module sub (
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input clk,
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output wire signed [2:0] sgn,
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output wire [2:0] unsgn,
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input signed [7:0] iss,
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input signed [7:0] isu,
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input [7:0] ius,
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input [7:0] iuu
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);
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assign sgn = 3'sh7;
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assign unsgn = 3'h7;
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("in: %x %x %x %x\n", iss, isu, ius, iuu);
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if (iss != 8'hff) $stop;
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if (isu != 8'h07) $stop;
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if (ius != 8'hff) $stop;
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if (iuu != 8'h07) $stop;
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`endif
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end
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endmodule
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