19 lines
393 B
Systemverilog
19 lines
393 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module sub (
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i
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);
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parameter N = 3;
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input [N : 0] i; // Note 3:0 conflicts until parameterize
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wire [2:0] i;
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endmodule
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module t;
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wire [2:0] i;
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sub #(.N(2)) sub (.i);
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endmodule
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