37 lines
741 B
Systemverilog
37 lines
741 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2003 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t_inst_first_b ( /*AUTOARG*/
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// Outputs
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o_seq_d1r, o_com, o2_com,
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// Inputs
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clk, i_seq, i_com, i2_com, wide_for_trace, wide_for_trace_2
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);
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// verilator inline_module
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input clk;
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input i_seq;
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output o_seq_d1r;
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input i_com;
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output o_com;
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input [1:0] i2_com;
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output [1:0] o2_com;
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input [127:0] wide_for_trace;
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input [127:0] wide_for_trace_2;
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/*AUTOREG*/
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reg o_seq_d1r;
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always @(posedge clk) begin
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o_seq_d1r <= ~i_seq;
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end
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wire [1:0] o2_com = ~i2_com;
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wire o_com = ~i_com;
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endmodule
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