60 lines
1.3 KiB
Systemverilog
60 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2003-2007 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc;
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initial cyc = 1;
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reg [31:0] long;
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reg [63:0] quad;
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wire [31:0] longout;
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wire [63:0] quadout;
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wire [7:0] narrow = long[7:0];
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sub sub ( /*AUTOINST*/
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// Outputs
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.longout(longout[31:0]),
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.quadout(quadout[63:0]),
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// Inputs
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.narrow(narrow[7:0]),
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.quad(quad[63:0])
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);
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always @(posedge clk) begin
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if (cyc != 0) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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long <= 32'h12345678;
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quad <= 64'h12345678_abcdef12;
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end
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if (cyc == 2) begin
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if (longout !== 32'h79) $stop;
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if (quadout !== 64'h12345678_abcdef13) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module sub (
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input [7:0] narrow,
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input [63:0] quad,
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output [31:0] longout,
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output [63:0] quadout
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);
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// verilator public_module
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`ifdef verilator
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assign longout = $c32("(", narrow, "+1)");
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assign quadout = $c64("(", quad, "+1)");
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`else
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assign longout = narrow + 8'd1;
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assign quadout = quad + 64'd1;
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`endif
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endmodule
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