49 lines
1.0 KiB
Systemverilog
49 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2012 Iztok Jeras
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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parameter SIZE = 8;
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integer cnt = 0;
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logic [SIZE-1:0] vld_for;
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logic vld_if = 1'b0;
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logic vld_else = 1'b0;
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genvar i;
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// event counter
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always @(posedge clk) begin
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cnt <= cnt + 1;
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end
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// finish report
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always @(posedge clk)
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if (cnt == SIZE) begin : \0escaped___name
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$write("*-* All Finished *-*\n");
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$finish;
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end : \0escaped___name
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generate
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for (i = 0; i < SIZE; i = i + 1) begin : generate_for
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always @(posedge clk) if (cnt == i) vld_for[i] <= 1'b1;
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end : generate_for
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endgenerate
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generate
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if (SIZE > 0) begin : generate_if_if
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always @(posedge clk) vld_if <= 1'b1;
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end : generate_if_if
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else begin : generate_if_else
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always @(posedge clk) vld_else <= 1'b1;
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end : generate_if_else
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endgenerate
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endmodule : t
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