44 lines
791 B
Systemverilog
44 lines
791 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t #(
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parameter PIPE = 4
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) ( /*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// These are ok
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sub #(.P_STOP(1)) u_sub1 ();
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sub #(.P_STOP(0)) u_sub0 ();
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genvar i;
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for (i = -1; i < 1; i++) begin : SUB_PIPE
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sub #(.P_STOP(i)) u_sub ();
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end
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always @(posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module sub #(
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parameter P_START = 1,
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parameter P_STOP = 0
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) ();
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initial begin
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for (int i = P_START; i >= P_STOP; --i) begin
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$display("%m %0d..%0d i=%0d", P_START, P_STOP, i);
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end
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end
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endmodule
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