48 lines
681 B
Systemverilog
48 lines
681 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2008 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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/// We define the modules in "backward" order.
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module d;
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endmodule
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module b;
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generate
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if (1) begin
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c c1 ();
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c c2 ();
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end
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endgenerate
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endmodule
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module c;
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generate
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if (1) begin
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d d1 ();
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d d2 ();
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end
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endgenerate
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endmodule
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module a;
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generate
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if (1) begin
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b b1 ();
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b b2 ();
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end
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endgenerate
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endmodule
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module t;
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a a1 ();
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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