91 lines
2.0 KiB
Systemverilog
91 lines
2.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2013 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc = 0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [3:0] datai = crc[3:0];
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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logic [3:0] datao; // From test of Test.v
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// End of automatics
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Test test ( /*AUTOINST*/
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// Outputs
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.datao(datao[3:0]),
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// Inputs
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.clk(clk),
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.datai(datai[3:0])
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);
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// Aggregate outputs into a single result vector
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wire [63:0] result = {60'h0, datao};
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// Test loop
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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if (cyc == 0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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end
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else if (cyc < 10) begin
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sum <= 64'h0;
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end
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else if (cyc < 90) begin
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end
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else if (cyc == 99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'h3db7bc8bfe61f983
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test (
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input logic clk,
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input logic [3:0] datai,
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output logic [3:0] datao
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);
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genvar i;
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parameter SIZE = 4;
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logic [SIZE:1][3:0] delay;
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always_ff @(posedge clk) begin
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delay[1][3:0] <= datai;
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end
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generate
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for (i = 2; i < (SIZE + 1); i++) begin
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always_ff @(posedge clk) begin
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delay[i][3:0] <= delay[i-1][3:0];
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end
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end
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endgenerate
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always_comb datao = delay[SIZE][3:0];
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endmodule
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