30 lines
568 B
Systemverilog
30 lines
568 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2021 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module s;
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parameter A = 0;
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generate
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if (A == 1) int i;
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else if (A == 2) int i;
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else int i;
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endgenerate
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generate
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if (A == 1) int i;
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else if (A == 2) int i;
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else int i;
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endgenerate
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endmodule
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module t;
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s #(0) s0 ();
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s #(1) s1 ();
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s #(2) s2 ();
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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