101 lines
2.3 KiB
Systemverilog
101 lines
2.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test for short-circuiting in generate "if"
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// that should not work.
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//
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// The given generate loops should attempt to access invalid bits of mask and
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// trigger errors.
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// is defined by SIZE. However since the loop range is larger, this only works
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// if short-circuited evaluation of the generate loop is in place.
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// This file ONLY is placed into the Public Domain.
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// SPDX-FileCopyrightText: 2012 Jeremy Bennett
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// SPDX-License-Identifier: CC0-1.0
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`define MAX_SIZE 3
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module t (
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input clk
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);
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// Set the parameters, so that we use a size less than MAX_SIZE
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test_gen #(
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.SIZE(2),
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.MASK(2'b11)
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) i_test_gen (
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.clk(clk)
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);
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// This is only a compilation test, so we can immediately finish
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always @(posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule // t
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module test_gen #(
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parameter SIZE = `MAX_SIZE,
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MASK = `MAX_SIZE'b0
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) (
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input clk
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);
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// Generate blocks that all have errors in applying short-circuting to
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// generate "if" conditionals.
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// Attempt to access invalid bits of MASK in different ways
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generate
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genvar g;
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for (g = 0; g < `MAX_SIZE; g = g + 1) begin
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if ((g < (SIZE + 1)) && MASK[g]) begin
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]);
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`endif
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end
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end
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end
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endgenerate
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generate
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for (g = 0; g < `MAX_SIZE; g = g + 1) begin
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if ((g < SIZE) && MASK[g+1]) begin
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]);
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`endif
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end
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end
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end
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endgenerate
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// Attempt to short-circuit bitwise AND
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generate
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for (g = 0; g < `MAX_SIZE; g = g + 1) begin
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if ((g < (SIZE)) & MASK[g]) begin
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("Bitwise AND generate if MASK [%1d] = %d\n", g, MASK[g]);
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`endif
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end
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end
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end
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endgenerate
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// Attempt to short-circuit bitwise OR
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generate
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for (g = 0; g < `MAX_SIZE; g = g + 1) begin
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if (!((g >= SIZE) | ~MASK[g])) begin
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("Bitwise OR generate if MASK [%1d] = %d\n", g, MASK[g]);
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`endif
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end
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end
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end
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endgenerate
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endmodule
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