64 lines
1.3 KiB
Systemverilog
64 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2007 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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`timescale 1ns / 1ps
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module t (
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input clk
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);
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integer cyc;
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initial cyc = 0;
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reg [63:0] crc;
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reg [31:0] sum;
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wire [8:0] Output;
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wire [8:0] Input = crc[8:0];
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assigns assigns ( /*AUTOINST*/
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// Outputs
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.Output(Output[8:0]),
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// Inputs
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.Input(Input[8:0])
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);
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x q=%x\n", $time, cyc, crc, sum);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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if (cyc == 0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 32'h0;
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end
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else if (cyc > 10 && cyc < 90) begin
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sum <= {sum[30:0], sum[31]} ^ {23'h0, crc[8:0]};
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end
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else if (cyc == 99) begin
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if (sum !== 32'he8bbd130) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module assigns (
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Input,
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Output
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);
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input [8:0] Input;
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output [8:0] Output;
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genvar i;
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generate
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for (i = 0; i < 8; i = i + 1) begin : ap
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assign Output[(i>0)?i-1 : 8] = Input[(i>0)?i-1 : 8];
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end
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endgenerate
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endmodule
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