48 lines
860 B
Systemverilog
48 lines
860 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Yutetsu TAKATSUKASA
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// SPDX-License-Identifier: CC0-1.0
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// bug5101
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module t;
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logic [1:0] in0, in1, out;
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logic sel;
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assign in0 = 1;
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assign in1 = 2;
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assign sel = 1'b1;
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initial begin
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$display("out:%d", out);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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bug5101 u_bug5101 (
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.in0,
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.in1,
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.sel,
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.out
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);
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endmodule
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module bug5101 (
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input wire [1:0] in0,
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input wire [1:0] in1,
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input wire sel,
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output logic [1:0] out
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);
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// verilator no_inline_module
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function logic [1:0] incr(input [1:0] in);
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logic [1:0] tmp;
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tmp = in + 1;
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return tmp;
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endfunction
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always_comb
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if (sel) out = in0;
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else out = incr(in1);
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endmodule
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