62 lines
1.6 KiB
Systemverilog
62 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2005 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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reg [7:0] crc;
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wire [61:59] ah = crc[5:3];
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wire [61:59] bh = ~crc[4:2];
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wire [41:2] al = {crc, crc, crc, crc, crc};
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wire [41:2] bl = ~{crc[6:0], crc[6:0], crc[6:0], crc[6:0], crc[6:0], crc[6:2]};
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reg sel;
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wire [61:28] q = (sel ? func(ah, al) : func(bh, bl));
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function [61:28] func;
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input [61:59] inh;
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input [41:2] inl;
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reg [42:28] func_mid;
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reg carry;
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begin
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carry = &inl[27:2];
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func_mid = {1'b0, inl[41:28]} + {14'b0, carry};
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func[61:59] = inh + {2'b0, func_mid[42]};
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func[58:42] = {17{func_mid[41]}};
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func[41:28] = func_mid[41:28];
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end
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endfunction
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integer cyc;
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initial cyc = 1;
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always @(posedge clk) begin
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//$write("%d %x\n", cyc, q);
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if (cyc != 0) begin
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cyc <= cyc + 1;
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sel <= ~sel;
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crc <= {crc[6:0], ~^{crc[7], crc[5], crc[4], crc[3]}};
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if (cyc == 1) begin
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sel <= 1'b1;
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crc <= 8'h12;
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end
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if (cyc == 2) if (q != 34'h100000484) $stop;
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if (cyc == 3) if (q != 34'h37fffeddb) $stop;
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if (cyc == 4) if (q != 34'h080001212) $stop;
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if (cyc == 5) if (q != 34'h1fffff7ef) $stop;
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if (cyc == 6) if (q != 34'h200000848) $stop;
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if (cyc == 7) if (q != 34'h380001ebd) $stop;
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if (cyc == 8) if (q != 34'h07fffe161) $stop;
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if (cyc == 9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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