108 lines
1.6 KiB
Systemverilog
108 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2003 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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reg [7:0] a, b;
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wire [7:0] z;
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mytop u0 (
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a,
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b,
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clk,
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z
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);
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integer cyc;
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initial cyc = 1;
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always @(posedge clk) begin
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if (cyc != 0) begin
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cyc <= cyc + 1;
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//$write("%d %x\n", cyc, z);
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if (cyc == 1) begin
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a <= 8'h07;
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b <= 8'h20;
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end
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if (cyc == 2) begin
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a <= 8'h8a;
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b <= 8'h12;
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end
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if (cyc == 3) begin
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if (z !== 8'hdf) $stop;
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a <= 8'h71;
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b <= 8'hb2;
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end
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if (cyc == 4) begin
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if (z !== 8'hed) $stop;
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end
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if (cyc == 5) begin
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if (z !== 8'h4d) $stop;
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end
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if (cyc == 9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule // mytop
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module inv (
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input [7:0] a,
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output wire [7:0] z
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);
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assign z = ~a;
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endmodule
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module ftest (
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input [7:0] a,
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b, // Test legal syntax
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input clk,
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output reg [7:0] z
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);
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wire [7:0] zi;
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inv u1 (
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.a(myadd(a, b)),
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.z(zi)
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);
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always @(posedge clk) begin
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z <= myadd(a, zi);
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end
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function [7:0] myadd;
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input [7:0] ina;
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input [7:0] inb;
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begin
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myadd = ina + inb;
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end
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endfunction // myadd
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endmodule // ftest
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module mytop (
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input [7:0] a,
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b,
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input clk,
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output [7:0] z
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);
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ftest u0 (
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a,
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b,
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clk,
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z
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);
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endmodule // mytop
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