52 lines
1017 B
Systemverilog
52 lines
1017 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2003 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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reg [31:0] r32;
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wire [3:0] w4;
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wire [4:0] w5;
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assign w4 = NUMONES_8(r32[7:0]);
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assign w5 = NUMONES_16(r32[15:0]);
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function [3:0] NUMONES_8;
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input [7:0] i8;
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reg [7:0] i8;
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begin
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NUMONES_8 = 4'b1;
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end
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endfunction // NUMONES_8
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function [4:0] NUMONES_16;
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input [15:0] i16;
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reg [15:0] i16;
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begin
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NUMONES_16 = (NUMONES_8(i16[7:0]) + NUMONES_8(i16[15:8]));
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end
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endfunction
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integer cyc;
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initial cyc = 1;
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always @(posedge clk) begin
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if (cyc != 0) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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r32 <= 32'h12345678;
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end
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if (cyc == 2) begin
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if (w4 !== 1) $stop;
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if (w5 !== 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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