25 lines
411 B
Systemverilog
25 lines
411 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2024 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic x;
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sub s (x);
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initial #1 x = 1;
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endmodule
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module sub (
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input x
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);
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initial
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fork
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begin
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@x;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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join_any
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endmodule
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