30 lines
507 B
Systemverilog
30 lines
507 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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int x = 100;
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task get_x(output int arg);
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arg = x;
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endtask
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endclass
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task automatic test;
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int o;
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Cls c = new;
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fork
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c.get_x(o);
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join_any
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if (o != 100) $stop;
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endtask
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module t;
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initial begin
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test();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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