106 lines
2.5 KiB
Systemverilog
106 lines
2.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2004 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc;
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initial cyc = 1;
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integer j;
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reg [63:0] cam_lookup_hit_vector;
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integer hit_count;
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always @( /*AUTOSENSE*/ cam_lookup_hit_vector) begin
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hit_count = 0;
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for (j = 0; j < 64; j = j + 1) begin
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hit_count = hit_count + {31'h0, cam_lookup_hit_vector[j]};
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end
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end
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integer hit_count2;
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always @( /*AUTOSENSE*/ cam_lookup_hit_vector) begin
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hit_count2 = 0;
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for (j = 63; j >= 0; j = j - 1) begin
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hit_count2 = hit_count2 + {31'h0, cam_lookup_hit_vector[j]};
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end
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end
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integer hit_count3;
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always @( /*AUTOSENSE*/ cam_lookup_hit_vector) begin
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hit_count3 = 0;
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for (j = 63; j > 0; j = j - 1) begin
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if (cam_lookup_hit_vector[j]) hit_count3 = hit_count3 + 32'd1;
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end
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end
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reg [127:0] wide_for_index;
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reg [31:0] wide_for_count;
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always @( /*AUTOSENSE*/ cam_lookup_hit_vector) begin
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wide_for_count = 0;
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for (
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wide_for_index = 128'hff_00000000_00000000;
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wide_for_index < 128'hff_00000000_00000100;
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wide_for_index = wide_for_index + 2
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) begin
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wide_for_count = wide_for_count + 32'h1;
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end
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end
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// While loop
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int w;
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initial begin
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while (w < 10) w = w + 1;
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if (w != 10) $stop;
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while (w < 20) begin
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w = w + 2;
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end
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while (w < 20) begin
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w = w + 99999;
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end // NEVER
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if (w != 20) $stop;
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end
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// Do-While loop
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int dw;
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initial begin
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do dw = dw + 1; while (dw < 10);
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if (dw != 10) $stop;
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do dw = dw + 2; while (dw < 20);
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if (dw != 20) $stop;
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do dw = dw + 5; while (dw < 20); // Once
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if (dw != 25) $stop;
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end
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always @(posedge clk) begin
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cam_lookup_hit_vector <= 0;
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if (cyc != 0) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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cam_lookup_hit_vector <= 64'h00010000_00010000;
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end
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if (cyc == 2) begin
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if (hit_count != 32'd2) $stop;
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if (hit_count2 != 32'd2) $stop;
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if (hit_count3 != 32'd2) $stop;
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cam_lookup_hit_vector <= 64'h01010010_00010001;
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end
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if (cyc == 3) begin
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if (hit_count != 32'd5) $stop;
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if (hit_count2 != 32'd5) $stop;
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if (hit_count3 != 32'd4) $stop;
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if (wide_for_count != 32'h80) $stop;
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end
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if (cyc == 9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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