46 lines
1.0 KiB
Systemverilog
46 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: on
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: off
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module t;
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int a, b;
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int sum;
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// Complicated assignment cases
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initial begin
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sum = 0;
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for (integer a = 0; a < 3;) begin
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a = a + 1;
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sum = sum + a;
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end
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`checkd(sum, 6);
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// foperator_assignment
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sum = 0;
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for (integer a = 0; a < 3; a = a + 1, sum += a);
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`checkd(sum, 6);
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// inc_or_dec_expression
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sum = 0;
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for (integer a = 0; a < 3; a++, ++sum);
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`checkd(sum, 3);
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// task_subroutine_call
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sum = 0;
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for (integer a = 0; a < 3; a++, sum += $clog2(a));
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`checkd(sum, 3);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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