21 lines
449 B
Systemverilog
21 lines
449 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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function automatic int f(int x);
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int n;
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for (int i = 0; i < x; ++i) begin
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++n;
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end
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return n;
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endfunction
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module t (
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output logic [f(4):0] o4, // Should simulate
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output logic [f(5):0] o5 // Should NOT simulate
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);
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endmodule
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