49 lines
996 B
Systemverilog
49 lines
996 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`ifdef verilator
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`define no_optimize(v) $c(v)
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`else
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`define no_optimize(v) (v)
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`endif
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// verilog_format: on
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virtual class Base;
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pure virtual function int get_param;
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endclass
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class Foo #(
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int N = 17
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) extends Base;
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function int get_param;
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return `no_optimize(N);
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endfunction
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endclass
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module t (
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input clk
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);
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localparam MAX = 128;
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Base q[$];
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generate
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// should result in many C++ files
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genvar i;
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for (i = 0; i < MAX; i++)
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initial begin
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automatic Foo #(i) item = new;
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q.push_back(item);
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end
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endgenerate
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always @(posedge clk) begin
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static int sum = 0;
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foreach (q[i]) sum += q[i].get_param();
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if (sum != MAX * (MAX - 1) / 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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