71 lines
1.2 KiB
Systemverilog
71 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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module test_mod (
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input reg clk,
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input reg reset,
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output integer result
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);
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always @(reset) begin
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result <= 1;
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end
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endmodule
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module Dut (
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input clk
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);
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int num;
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integer result1;
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integer result2;
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reg reset1;
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reg reset2;
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initial begin
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reset1 = $random;
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reset2 = $random;
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end
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always @(posedge clk) begin
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num <= num + 1;
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if (num == 5) begin
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reset1 <= 1'b1;
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end
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if (num == 10) begin
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// display to prevent optimalization
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$display("result1: %d", result1);
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$display("result2: %d", result2);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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always @(reset1) begin
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reset2 <= t.reset;
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end
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test_mod t (
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.clk(clk),
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.reset(reset1),
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.result(result1)
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);
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test_mod t2 (
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.clk(clk),
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.reset(reset2),
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.result(result2)
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);
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endmodule
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module Dut_wrapper (
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input clk
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);
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Dut d (.clk(clk));
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Dut d2 (.clk(clk));
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endmodule
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module t (
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input clk
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);
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Dut_wrapper d_w (.clk(clk));
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endmodule
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