35 lines
585 B
Systemverilog
35 lines
585 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module x;
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event a;
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event b;
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bit ok = 0;
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task do_the_job();
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static bit first = 1;
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if (first) begin
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first = 0;
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@a;
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ok = 1;
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end
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else begin
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->a;
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end
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endtask
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initial begin
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#1 ->b;
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#100;
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if (!ok) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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always @b do_the_job();
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always @b do_the_job();
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endmodule
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