34 lines
537 B
Systemverilog
34 lines
537 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module x;
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event a;
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int counter = 0;
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initial begin
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fork
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begin
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@a;
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->a;
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@a;
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counter++;
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end
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join_none
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#1;
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->a;
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end
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always begin
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@a;
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->a;
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@a;
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counter++;
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end
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final begin
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if (counter != 1) $stop;
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$write("*-* All Finished *-*\n");
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end
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endmodule
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