20 lines
489 B
Systemverilog
20 lines
489 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t_emit_accessors (
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input bit in1,
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input bit in2,
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input logic [31:0] in3,
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input logic [31:0] in4,
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output bit out1,
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output logic [31:0] out2,
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output logic [77:0] out3
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);
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assign out1 = in1 & in2;
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assign out2 = in3 & in4;
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assign out3 = 1;
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endmodule
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