164 lines
2.8 KiB
Systemverilog
164 lines
2.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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function automatic bit test_1;
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int iterations = 0;
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do begin
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iterations++;
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break;
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end while (1);
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return iterations == 1;
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endfunction
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function automatic bit test_2;
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int iterations = 0;
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do begin
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break;
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iterations++;
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end while (1);
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return iterations == 0;
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endfunction
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function bit test_3;
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do break; while (1);
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return 1'b1;
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endfunction
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function automatic bit test_4;
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int incr = 0;
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do begin
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incr++;
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break;
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incr++;
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end while (1);
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return incr == 1;
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endfunction
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function automatic bit test_5;
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int incr = 0;
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do begin
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do incr++; while (incr < 9);
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incr++;
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break;
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incr++;
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end while (1);
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return incr == 10;
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endfunction
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function automatic bit test_6;
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int incr = 0;
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do begin
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do begin
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incr += 1;
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incr += 2;
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end while (incr < 9);
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incr++;
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break;
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incr++;
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end while (1);
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return incr == 10;
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endfunction
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function automatic bit test_7;
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int incr = 0;
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do begin
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do begin
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incr += 1;
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break;
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incr += 2;
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end while (incr < 9);
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incr++;
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break;
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incr++;
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end while (1);
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return incr == 2;
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endfunction
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function automatic bit test_8;
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int incr = 0;
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do begin
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incr++;
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continue;
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incr++;
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end while (0);
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return incr == 1;
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endfunction
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function automatic bit test_9;
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int incr = 0;
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do begin
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incr++;
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continue;
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incr++;
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end while (incr < 5);
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return incr == 5;
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endfunction
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function automatic bit test_10;
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do begin
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continue;
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end while (0);
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return 1'b1;
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endfunction
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function automatic bit test_11;
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int incr = 0;
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do begin
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do incr++; while (0);
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incr++;
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continue;
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incr++;
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end while (incr < 11);
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return incr == 12;
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endfunction
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function automatic bit test_12;
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int incr = 0;
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do begin
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do begin
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incr++;
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continue;
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incr++;
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end while (0);
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incr++;
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continue;
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incr++;
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end while (incr < 11);
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return incr == 12;
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endfunction
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always @(posedge clk) begin
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bit [11:0] results;
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results = {
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test_1(),
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test_2(),
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test_3(),
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test_4(),
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test_5(),
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test_6(),
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test_7(),
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test_8(),
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test_9(),
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test_10(),
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test_11(),
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test_12()
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};
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if (results == '1) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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$write("Results: %b\n", results);
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$stop;
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end
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end
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endmodule
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