31 lines
638 B
Systemverilog
31 lines
638 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2021 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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int cyc = 0;
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always @(posedge clk)++cyc;
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reg [15 : 0] t2;
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always @(posedge clk) begin
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if (cyc == 0) begin
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t2 <= 16'd0;
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end
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else if (cyc == 2) begin
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t2 <= 16'habcd;
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end
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else if (cyc == 4) begin
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$display("abcd=%x", t2);
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$display("ab0d=%x", {t2[15:8], 4'd0, t2[3:0]});
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$write("*-* All Finished *-*\n");
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$finish(32'd0);
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end
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end
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endmodule
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