19 lines
487 B
Systemverilog
19 lines
487 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2003 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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reg [40:0] disp;
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initial disp = 41'ha_bbbb_cccc;
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initial begin
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// Display formatting
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$display("%x"); // Too few
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$display("%x", disp, disp); // Too many
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$display("%q"); // Bad escape
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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