15 lines
304 B
Systemverilog
15 lines
304 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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module t(
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input rstn
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);
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default disable iff (!rstn);
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default disable iff (!rstn);
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endmodule
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