70 lines
2.0 KiB
Systemverilog
70 lines
2.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module t;
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bit clk = 1'b0;
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always #5 clk = ~clk;
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logic [63:0] crc = 64'h5aef0c8d_d70a4497;
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localparam N = 16;
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// Generate variables
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for (genvar n = 0; n < N; ++n) begin : vars
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logic [n:0] tmp;
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logic out;
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end
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// Generate logic
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for (genvar n = 0; n < N; ++n) begin
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if (n == 0) begin
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assign vars[n].tmp = ~crc[n];
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assign vars[n].out = vars[n].tmp[n];
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end
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else begin
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assign vars[n].tmp = {~crc[n], vars[n-1].tmp};
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assign vars[n].out = vars[n].tmp[n] ^ vars[n-1].out;
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end
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end
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// Would create cycle:
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wire [3:0] danger_src = {crc[4:3], crc[1:0]};
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wire [1:0] danger_sel = danger_src[2:1];
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wire [5:0] danger_dst = {~danger_sel, danger_src};
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// Sink has no other sinks
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wire [3:0] noother_src = {crc[5:4], crc[2:1]};
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wire [1:0] noother_sel = noother_src[2:1];
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wire [7:0] noother_dst = {crc[9:6], noother_src}; // singal intentianally unused
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int cyc;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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//$display("%16b %16b", ~crc[N-1:0], vars[N-1].tmp);
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//$display("%16b %16b", ^(~crc[N-1:0]), vars[N-1].out);
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// Check halfway through, this prevents pushing sels past this point
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`checkh(vars[N/2].tmp, ~crc[N/2:0]);
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`checkh(vars[N/2].out, ^(~crc[N/2:0]));
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// Check final value
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`checkh(vars[N-1].tmp, ~crc[N-1:0]);
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`checkh(vars[N-1].out, ^(~crc[N-1:0]));
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if (cyc == 10) begin
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// Observe danger_dst so it's not eliminated
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$display("%0b", danger_dst);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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