67 lines
2.1 KiB
Systemverilog
67 lines
2.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH.
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// SPDX-License-Identifier: CC0-1.0
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// Test static constraint_mode() support per IEEE 1800-2017 Section 18.4, 18.8
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// Static constraint mode should be shared across all instances.
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class StaticConstraintTest;
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rand bit [7:0] value;
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// Static constraint - shared across all instances
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static constraint static_con {value inside {[10 : 15]};}
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// Non-static constraint for comparison
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constraint instance_con {value > 5;}
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endclass
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module t;
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StaticConstraintTest obj1, obj2;
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initial begin
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obj1 = new();
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obj2 = new();
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// Test 1: Verify static constraint_mode getter works
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if (obj1.static_con.constraint_mode() != 1) $stop;
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if (obj2.static_con.constraint_mode() != 1) $stop;
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// Test 2: Disable static constraint on one instance
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obj1.static_con.constraint_mode(0);
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// Verify the state is shared across all instances
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if (obj1.static_con.constraint_mode() != 0) $stop;
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if (obj2.static_con.constraint_mode() != 0) $stop;
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// Test 3: Re-enable static constraint via different instance
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obj2.static_con.constraint_mode(1);
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// Verify state is updated for all instances
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if (obj1.static_con.constraint_mode() != 1) $stop;
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if (obj2.static_con.constraint_mode() != 1) $stop;
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// Test 4: Verify randomization respects constraint mode when enabled
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obj1.static_con.constraint_mode(1);
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obj1.instance_con.constraint_mode(1);
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for (int i = 0; i < 10; i++) begin
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void'(obj1.randomize());
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if (!(obj1.value inside {[10 : 15]})) $stop;
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if (!(obj1.value > 5)) $stop;
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end
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// Test 5: Disable static constraint and verify randomization changes
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obj1.static_con.constraint_mode(0);
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// With static_con disabled, value only needs to be > 5
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for (int i = 0; i < 10; i++) begin
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obj1.value = 1; // Reset to low value
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void'(obj1.randomize());
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if (!(obj1.value > 5)) $stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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