27 lines
511 B
Systemverilog
27 lines
511 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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rand bit [7:0] x;
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rand bit [7:0] y;
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function bit [7:0] complex_func(bit [7:0] m);
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if (m > 128) return m;
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else return m + 1;
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endfunction
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constraint c {x <= complex_func(y);}
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endclass
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module t;
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Cls obj;
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initial begin
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obj = new;
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void'(obj.randomize());
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end
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endmodule
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