59 lines
1.5 KiB
Systemverilog
59 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); `stop; end while(0);
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// verilog_format: on
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class FuncConstraintTest;
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rand bit [7:0] value;
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rand bit [7:0] mask;
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function bit [7:0] get_min_value(bit [7:0] m);
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return m & 8'hF0;
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endfunction
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function bit [7:0] get_max_value(bit [7:0] m);
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return m | 8'h0F;
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endfunction
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constraint func_con {
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mask inside {[8'h10 : 8'hF0]};
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value >= get_min_value(mask);
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value <= get_max_value(mask);
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}
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function new();
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endfunction
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endclass
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module t;
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FuncConstraintTest fct;
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int rand_ok;
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bit [7:0] min_val;
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bit [7:0] max_val;
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initial begin
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fct = new();
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repeat (10) begin
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rand_ok = fct.randomize();
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`checkd(rand_ok, 1)
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`check_range(fct.mask, 8'h10, 8'hF0)
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min_val = fct.get_min_value(fct.mask);
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max_val = fct.get_max_value(fct.mask);
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`check_range(fct.value, min_val, max_val)
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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