23 lines
481 B
Systemverilog
23 lines
481 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// Test: non-constant control in $countbits inside constraint (unsupported)
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class Packet;
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rand bit [7:0] value;
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bit ctrl;
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constraint cons {$countbits(value, ctrl) == 3;}
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endclass
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module t;
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Packet p;
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initial begin
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p = new;
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void'(p.randomize());
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end
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endmodule
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