46 lines
962 B
Systemverilog
46 lines
962 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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`define check_rand(cl, field, cond) \
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begin \
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automatic longint prev_result; \
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automatic int ok; \
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if (!bit'(cl.randomize())) $stop; \
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prev_result = longint'(field); \
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if (!(cond)) $stop; \
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repeat(9) begin \
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longint result; \
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if (!bit'(cl.randomize())) $stop; \
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result = longint'(field); \
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if (!(cond)) $stop; \
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if (result != prev_result) ok = 1; \
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prev_result = result; \
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end \
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if (ok != 1) $stop; \
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end
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class Cls;
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int d;
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rand int y;
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rand bit i;
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constraint q {
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if (i) {
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((d == 0) ? y == 0 : 1'b1);
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}
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}
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endclass
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module t;
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Cls cls = new;
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initial begin
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`check_rand(cls, cls.y, cls.i == 0 || cls.y == 0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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