46 lines
986 B
Systemverilog
46 lines
986 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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module mod;
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bit clk = 1'b0;
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bit inp = 1'b0;
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clocking cb @(posedge clk);
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input #3 inp;
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endclocking
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always @(posedge clk) inp <= 1'b1;
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always #1 clk = ~clk;
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endmodule
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module main;
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bit clk = 1'b0;
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bit inp = 1'b0;
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always begin
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#2 if (t.mod1.cb.inp != 1'b0) $stop;
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if (t.main1.cbb.inp != 1'b0) $stop;
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if (t.main2.cbb.inp != 1'b0) $stop;
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#4;
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if (t.mod1.cb.inp != 1'b1) $stop;
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if (t.main1.cbb.inp != 1'b1) $stop;
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if (t.main2.cbb.inp != 1'b1) $stop;
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end
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clocking cbb @(posedge clk);
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input #3 inp;
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endclocking
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always @(posedge clk) inp <= 1'b1;
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always #1 clk = ~clk;
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endmodule
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module t;
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main main1 ();
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mod mod1 ();
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main main2 ();
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initial begin
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#7;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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