17 lines
340 B
Systemverilog
17 lines
340 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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default clocking @(posedge clk);
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endclocking
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default clocking @(posedge clk);
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endclocking
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endmodule
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