52 lines
1.0 KiB
Systemverilog
52 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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// verilator lint_off MULTIDRIVEN
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module t ( /*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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logic [31:0] lhs1, lhs2, rhs;
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logic cond = 0;
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always_comb lhs1 = rhs;
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assign lhs2 = rhs;
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always @(posedge clk) rhs = '1;
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always @(negedge clk) begin
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if (cond) begin
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force lhs1 = 'hdeadbeef;
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force lhs2 = 'hfeedface;
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end
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else begin
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release lhs1;
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release lhs2;
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end
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end
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int cyc = 0;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 0) cond <= 1;
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if (cyc == 3) cond <= 0;
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if (cyc > 1 && cyc < 4) begin
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if (lhs1 != 'hdeadbeef) $stop;
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if (lhs2 != 'hfeedface) $stop;
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end
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if (cyc > 4 && cyc < 8) begin
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if (lhs1 != '1) $stop;
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if (lhs2 != '1) $stop;
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end
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if (cyc >= 8) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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