43 lines
783 B
Systemverilog
43 lines
783 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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class Base;
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int k = 3;
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function new(int x);
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k = x;
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endfunction
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protected function int get_x_base();
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Base f = this;
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return 7;
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endfunction
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endclass
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class Foo extends Base;
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function new(int x);
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super.new(x);
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endfunction
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protected function int get_x();
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Foo f = this;
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return get_x_base();
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endfunction
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endclass
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class Bar extends Foo;
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function new();
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super.new(get_x());
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endfunction
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endclass
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module top;
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initial begin
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static Bar b = new();
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if (b.k != 7) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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