12 lines
384 B
Systemverilog
12 lines
384 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Not super-sensical to have checker without module, but useful for --lint-only
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checker check_equal (bit clk, int a, int b);
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assert property (@(posedge clk) a == b);
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endchecker
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