24 lines
518 B
Systemverilog
24 lines
518 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic [7:0] smaller;
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logic [15:0] bigger;
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typedef logic [15:0] bigger_t;
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initial begin
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smaller = 8'hfa;
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bigger = bigger_t'(signed'(smaller));
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$display("%x", bigger); // NOCOMMIT
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if (bigger != 16'hfffa) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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