19 lines
402 B
Systemverilog
19 lines
402 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t #(
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parameter type data_t = logic
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) (
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input data_t [7:0] in_data
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);
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typedef data_t [7:0] in_data_t;
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in_data_t out_data;
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always_comb out_data = in_data_t'(in_data);
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endmodule
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