95 lines
2.2 KiB
Systemverilog
95 lines
2.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2009 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc = 0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [2:0] in = (crc[1:0] == 0 ? 3'd0 : crc[1:0] == 0 ? 3'd1 : crc[1:0] == 0 ? 3'd2 : 3'd4);
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [31:0] out; // From test of Test.v
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// End of automatics
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Test test ( /*AUTOINST*/
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// Outputs
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.out(out[31:0]),
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// Inputs
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.clk(clk),
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.in(in[2:0])
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);
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// Aggregate outputs into a single result vector
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wire [63:0] result = {32'h0, out};
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// Test loop
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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if (cyc == 0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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end
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else if (cyc < 10) begin
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sum <= 64'h0;
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end
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else if (cyc < 90) begin
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end
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else if (cyc == 99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'h704ca23e2a83e1c5
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test ( /*AUTOARG*/
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// Outputs
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out,
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// Inputs
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clk,
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in
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);
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// Replace this module with the device under test.
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//
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// Change the code in the t module to apply values to the inputs and
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// merge the output values into the result vector.
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input clk;
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input [2:0] in;
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output reg [31:0] out;
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localparam ST_0 = 0;
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localparam ST_1 = 1;
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localparam ST_2 = 2;
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always @(posedge clk) begin
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case (1'b1) // synopsys parallel_case
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in[ST_0]: out <= 32'h1234;
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in[ST_1]: out <= 32'h4356;
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in[ST_2]: out <= 32'h9874;
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default: out <= 32'h1;
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endcase
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end
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endmodule
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