33 lines
551 B
Systemverilog
33 lines
551 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module test1 (
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input logic b
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);
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logic do_something;
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assign do_something = b;
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endmodule
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module test2 (
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input bit b[2]
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);
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bit do_something[2];
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assign do_something = b;
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endmodule
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module t (
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input logic a[2] // unpacked array
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);
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logic b[2];
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assign b = a;
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test1 i_test1 (.b);
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test2 i_test2 (.b);
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endmodule
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