48 lines
770 B
Systemverilog
48 lines
770 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2022-2025 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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int cyc = 0;
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logic val = 0;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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val = ~val;
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end
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property p_alw;
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always [2:5] a;
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endproperty
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property p_s_alw;
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s_always [2:5] a;
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endproperty
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property p_ev;
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eventually [2:5] a;
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endproperty
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property p_evc;
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eventually [2] a;
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endproperty
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property p_s_ev;
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s_eventually [2:5] a;
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endproperty
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property p_s_alw_ev;
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always s_eventually [2:5] a;
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endproperty
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property p_s_ev_alw;
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s_eventually always [2:5] a;
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endproperty
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endmodule
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