64 lines
1.5 KiB
Systemverilog
64 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2003 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc;
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initial cyc = 1;
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reg posedge_wr_clocks;
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reg prev_wr_clocks;
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reg [31:0] m_din;
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reg [31:0] m_dout;
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always @(negedge clk) begin
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prev_wr_clocks = 0;
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end
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reg comb_pos_1;
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reg comb_prev_1;
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always @( /*AS*/ clk or posedge_wr_clocks or prev_wr_clocks) begin
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comb_pos_1 = (clk & ~prev_wr_clocks);
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comb_prev_1 = comb_pos_1 | posedge_wr_clocks;
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comb_pos_1 = 1'b1;
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end
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always @(posedge clk) begin
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posedge_wr_clocks = (clk & ~prev_wr_clocks); //surefire lint_off_line SEQASS
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prev_wr_clocks = prev_wr_clocks | posedge_wr_clocks; //surefire lint_off_line SEQASS
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if (posedge_wr_clocks) begin
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//$write("[%0t] Wrclk\n", $time);
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m_dout <= m_din;
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end
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end
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always @(posedge clk) begin
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if (cyc != 0) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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$write(" %x\n", comb_pos_1);
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m_din <= 32'hfeed;
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end
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if (cyc == 2) begin
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$write(" %x\n", comb_pos_1);
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m_din <= 32'he11e;
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end
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if (cyc == 3) begin
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m_din <= 32'he22e;
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$write(" %x\n", comb_pos_1);
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if (m_dout != 32'hfeed) $stop;
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end
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if (cyc == 4) begin
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if (m_dout != 32'he11e) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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