64 lines
1.3 KiB
Systemverilog
64 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2004 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc;
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initial cyc = 1;
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reg [31:0] a, b, c, d, e, f, g, h;
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always @(*) begin // Test Verilog 2001 (*)
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// verilator lint_off COMBDLY
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c <= a | b;
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// verilator lint_on COMBDLY
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end
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always @(posedge (clk)) begin // always bug 2008/4/18
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d <= a | b;
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end
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always @((d)) begin // always bug 2008/4/18
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e = d;
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end
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parameter CONSTANT = 1;
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always @(e, 1'b0, CONSTANT) begin // not technically legal, see bug412
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f = e;
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end
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always @(1'b0, CONSTANT, f) begin // not technically legal, see bug412
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g = f;
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end
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always @({CONSTANT,
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g
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})
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begin // bug745
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h = g;
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end
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//always @ ((posedge b) or (a or b)) begin // note both illegal
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always @(posedge clk) begin
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if (cyc != 0) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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a <= 32'hfeed0000;
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b <= 32'h0000face;
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end
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if (cyc == 2) begin
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if (c != 32'hfeedface) $stop;
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end
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if (cyc == 3) begin
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if (h != 32'hfeedface) $stop;
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end
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if (cyc == 7) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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